1. Field of the Invention
This invention relates to ferroelectric memories, and more particularly to a ferroelectric memory formed by cells each having two ferroelectric capacitors and two pass transistors wherein these two ferroelectric capacitors have their one ends connected respectively to first and second bit lines through pass transistors.
2. Description of the Prior Art
FIG. 13 shows a conventional ferroelectric memory 1 of a structure having two transistors and two capacitors. The ferroelectric memory 1 includes ferroelectric capacitors C1, C2 held in opposite polarization states to each other. When reading data, a pulse PL as shown in FIG. 14(B) is applied onto a plate line PL in a state that a pulse as shown in FIG. 14(A) is applied onto a word line WL to turn on transistors T1 and T2. This gives rise to respective voltages on the first bit line BL and the second bit line BL/(/ means inversion) correspondingly to the polarization states of the capacitors C1, C2. Because the capacitors C1, C2 are differently polarized from each other, there appears a difference in voltage between the first bit line BL and the second bit line BL/. Based on this, it is possible to determine whether the data is "0" or "1".
However, the data reading as above is so-called destructive read-out, wherein the polarization on the capacitor C1, C2 is destroyed by the pulse CL applied through the plate line PL. Due to this, data must be re-written by applying a pulse PL again onto the plate line PL. However, a plurality of cells are built on the plate line, requiring a high power to drive these cell capacitors.